1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device and writing method for the nonvolatile semiconductor memory device.
2. Discussion of the Related Art
Semiconductor memory devices may be either volatile semiconductor memory devices or nonvolatile semiconductor memory devices. Volatile semiconductor memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM). Volatile semiconductor memory devices are capable of fast reading and writing but stored information disappears when external power supply is interrupted. Nonvolatile semiconductor memory devices include mask read-only memory (MROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). Nonvolatile semiconductor memory devices retain information even when external power supply is interrupted. Accordingly, nonvolatile semiconductor memory devices are used to store information that should be retained regardless of the supply of power.
With respect to MROM, PROM, and EPROM, it is not easy for normal users to change stored information since erase and write operations cannot be freely performed. On the other hand, EEPROM enables electrical erase and write operations and is thus increasingly used where memory is continuously update or where memory is part of an auxiliary memory device. Particularly, flash EEPROM (hereinafter, referred to as a flash memory device) has a higher degree of integration than other existing forms of EEPROM and is thus often used as a large-capacity auxiliary memory device. When data is written to or read from a memory cell array in such EEPROM, a page buffer may be used in order to perform a write or read operation in units of pages.
FIG. 1 is a schematic functional block diagram of a conventional nonvolatile semiconductor memory device 10. Referring to FIG. 1, a controller 1 included in the nonvolatile semiconductor memory device 10 (e.g., EEPROM) receives externally input data DATA and an address ADDR indicating a position where the input data DATA will be written to in a cell array 5. The input data DATA may be temporarily stored in a page buffer 6 via a Y-decoder 7. The address ADDR may be temporarily stored in an address latch unit 2.
The address latch unit 2 may include an X-address latch 8 and a Y-address latch 9. The address ADDR may be divided into an X-address and a Y-address, which may be stored in the X-address latch 8 and the Y-address latch 9, respectively. In addition, the stored X-address and the stored Y-address may be respectively converted by a pre-decoder 3 into a row selection signal and a column selection signal for selecting a cell in the cell array 5. The row selection signal and the column selection signal may be output to an X-decoder 4 and the Y-decoder 7, respectively. The X-decoder 4 receives the row selection signal output from the pre-decoder 3 and selects a wordline corresponding to the row selection signal. The Y-decoder 7 receives the column selection signal and loads data DATA corresponding to the column selection signal to the page buffer 6.
The controller 1 may perform a write operation by controlling the page buffer 6 and a high-voltage generator (not shown) to perform an erase operation and a program operation on a memory cell corresponding to a wordline selected by the X-decoder 4 and a bitline selected by the Y-decoder. Accordingly the data DATA loaded to the page buffer 6 is written to the cell array 5.
However, according to this conventional writing method, the data DATA cannot be written to an exact address desired by a user when the data is sufficiently large to be written over two wordlines. For example, where there are 8 memory cells on a single wordline, the page buffer 6 has a size of 8, a user may want to write data D1, D2, D3, D4, D5, D6, D7, and D8 starting from a fifth memory cell on a first wordline. The data D1, D2, D3, and D4 should be stored in fifth, sixth, seventh, and eighth memory cells on the first wordline, and therefore, the data D1, D2, D3, and D4 are stored in fifth, sixth, seventh, and eighth latches of the page buffer 6. Since the data starting from D5 should be written to a second wordline, the X-decoder 4 selects the second wordline and the data D5, D6, D7, and D8 are stored in first, second, third, and fourth latches of the page buffer 6. Accordingly, the data loaded to the page buffer 6 is arranged in the following order: D5, D6, D7, D8, D1, D2, D3, and D4 and the X-decoder 4 selects the second wordline. As a result, the data is written to the second wordline in the following order: D5, D6, D7, D8, D1, D2, D3, and D4.
Accordingly, when writing data of a size equal to the page buffer, the user should always set a start address to the first address of a predetermined wordline. Otherwise all data loaded to the page buffer 6 are written to a last wordline as described above, and eventually, the data is written to unexpected places. As a result, the user may have to set the start address so that writing is performed starting from the first cell on a wordline.